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 DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
MBD128
BF1102; BF1102R Dual N-channel dual gate MOS-FETs
Product specification Supersedes data of 1999 Jul 01 2000 Apr 11
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
FEATURES * Two low noise gain controlled amplifiers in a single package * Specially designed for 5 V applications * Superior cross-modulation performance during AGC * High forward transfer admittance * High forward transfer admittance to input capacitance ratio. APPLICATIONS Gain controlled low noise amplifier for VHF and UHF applications such as television tuners and professional communications equipment. DESCRIPTION The BF1102 and BF1102R are both two equal dual gate MOS-FETs which have a shared source pin and a shared gate 2 pin. Both devices have interconnected source and substrate; an internal bias circuit enables DC stabilization and a very good cross-modulation performance at 5 V supply voltage; integrated diodes between the gates and source protect against excessive input voltage surges. Both devices have a SOT363 micro-miniature plastic package. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS PINNING - SOT363
BF1102; BF1102R
DESCRIPTION PIN BF1102 1 2 3 4 5 6 gate 1 (1) gate 2 (1 and 2) drain (1) drain (2) gate 1 (2) BF1102R gate 1 (1) source (1 and 2) drain (1) drain (2) gate 1 (2)
source (1 and 2) gate 2 (1 and 2)
handbook, halfpage
g2 (1, 2)
6
5
4 g1 (1) AMP1 d (1)
g1 (2) 1 2 3 BF1102 marking code: W1. BF1102R marking code: W2-.
AMP2
d (2)
s (1, 2)
MBL029
Fig.1 Simplified outline and symbol.
MIN. - -
TYP. - - - 43 2.8 30 2 - -
MAX.
UNIT
Per MOS-FET unless otherwise specified VDS ID Ptot yfs Cig1-s Crss F Xmod Tj Note 1. Ts is the temperature at the soldering point of the source lead. CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 2000 Apr 11 2 drain-source voltage drain current (DC) total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature Ts 102 C; note 1 ID = 15 mA ID = 15 mA f = 1 MHz f = 800 MHz 7 40 200 - 3.6 50 2.8 - 150 V mA mW mS pF fF dB dBV C
- 36 - - - -
input level for k = 1% at 40 dB AGC 100
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS - - - - Ts 102 C -
BF1102; BF1102R
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified VDS ID IG1 IG2 Ptot Tstg Tj drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature 7 40 10 10 200 +150 150 V mA mA mA mW C C
-65 -
THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 240 UNIT K/W
handbook, halfpage
250
MGS359
Ptot (mW)
200
150
100
50
0 0 50 100 150 Ts (C) 200
Fig.2 Power derating curve.
2000 Apr 11
3
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS VG1-S = VG2-S = 0; ID = 10 A VGS = VDS = 0; IG1-S = 10 mA VGS = VDS = 0; IG2-S = 5 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VDS = 5 V; VG2-S = 4 V; ID = 100 A VDS = 5 V; VG1-S = 4 V; ID = 100 A
BF1102; BF1102R
MIN.
MAX. - 15 15 1.5 1.5 1 1.2 20 50 20
UNIT
Per MOS-FET unless otherwise specified V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S Note 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F Xmod PARAMETER Tj = 25 C f = 1 MHz f = 1 MHz; (note 2) f = 1 MHz f = 1 MHz f = 800 MHz; YS = YS opt fw = 50 MHz; funw = 60 MHz; (note 3) input level for k = 1% at 0 dB AGC input level for k = 1% at 40 dB AGC Notes 1. Not used MOS-FET: VG1-S = 0; VDS = 0. 2. Gate 2 capacitance of both MOS-FETs. 3. Measured in test circuit of Fig.20. 85 100 - - - - dBV dBV CONDITIONS MIN. TYP. MAX. UNIT drain-source breakdown voltage gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current 7 6 6 0.5 0.5 0.3 0.3 12 - - V V V V V V V mA nA nA
VG2-S = 4 V; VDS = 5 V; RG = 120 k; note 1 VG1-S = 5 V; VG2-S = VDS = 0 VG2-S = 5 V; VG1-S = VDS = 0
Per MOS-FET unless otherwise specified (note 1) forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance noise figure cross-modulation 36 2 - - - - 43 2.8 - 1.6 30 2 50 3.6 7 2.5 50 2.8 mS pF pF pF fF dB
2000 Apr 11
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
ALL GRAPHS FOR ONE MOS-FET
BF1102; BF1102R
handbook, halfpage
30
MGS360
VG2-S = 4 V 3.5 V 3V
2.5 V
handbook, halfpage
30
MGS361
ID (mA) 20
ID (mA) 2V 20
VG1-S = 1.5 V
1.4 V 1.3 V 1.2 V
10
1.5 V
10 1.1 V 1V
0 0 0.4 0.8 1.2 1.6
1V 2.0 2.4 VG1-S (V)
0 0 2 4 6 8 10 VDS (V)
VDS = 5 V. Tj = 25 C.
VG2-S = 4 V. Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
handbook, halfpage
160
MGS362
IG1 (A) 120
VG2-S = 4 V 3.5 V
handbook, halfpage
50 |yfs | 40
MGS363
VG2-S = 4 V 3.5 V 3V
(mS)
3V 30 80 2.5 V 20 40 2V 10 2V 0 0 0.5 1 1.5 2 2.5 VG1-S (V) 2.5 V
0 0 10 20 ID (mA) 30
VDS = 5 V. Tj = 25 C.
VDS = 5 V. Tj = 25 C.
Fig.5
Gate 1 current as a function of gate 1 voltage; typical values.
Fig.6
Forward transfer admittance as a function of drain current; typical values.
2000 Apr 11
5
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
handbook, halfpage
25 ID (mA) 20
MGS364
handbook, halfpage
15
MGS365
ID (mA) 10
15
10 5 5
0 0 20 40 I G1 (A) 60
0 0 1 2 3 4 5 VGG (V)
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.20.
Fig.7
Drain current as a function of gate 1 current; typical values.
Fig.8
Drain current as a function of gate 1 supply voltage (= VGG); typical values.
handbook, halfpage
30
MGS366
MGS367
RG1 = 47 k
68 k 82 k 100 k 120 k
handbook, halfpage
20
ID (mA)
ID (mA)
VG1-S = 5 V 4.5 V 4V
16
20
3.5 V 150 k 180 k 220 k 8 12 3V
10 4
0 0 2 4 6 8 10 VGG = VDS (V)
0 0 2 4 VG2-S (V) 6
VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.20.
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.20.
Fig.9
Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values.
Fig.10 Drain current as a function of gate 2 voltage; typical values.
2000 Apr 11
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
handbook, halfpage
40
MGS368
handbook, halfpage gain
0
MCD968
I G1 (A) 30
VG1-S = 5 V 4.5 V 4V
reduction (dB) -10
-20
20
3.5 V 3V -30
10 -40
0 0 2 4 VG2-S (V) 6
-50
0
1
2
3
VAGC (V)
4
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C; RG1 = 120 k (connected to VGG); see Fig.20.
Fig.11 Gate 1 current as a function of gate 2 voltage; typical values.
Fig.12 Typical gain reduction as a function of the AGC voltage; see Fig.20.
handbook, halfpage
120
MGS369
handbook, halfpage
20
MCD969
Vunw (dB V) 110
ID (mA)
16
12 100 8 90 4
80 0 20 40 60 gain reduction (dB)
0 0 10 20 30 40 50 gain reduction (dB)
VDS = 5 V; VGG = 5 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C; RG1 = 120 k (connected to VGG); see Fig.20.
Fig.13 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values.
Fig.14 Drain current as a function of gain reduction; typical values.
2000 Apr 11
7
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
102 handbook, halfpage yis (mS)
MGS370
103 handbook, halfpage yrs (mS) 102 rs
MCD970
-103 rs (deg) -102
10
bis 1 g is 10
yrs -10
10 -1 10
102
f (MHz)
103
1 10
102 f (MHz)
-1 103
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.15 Input admittance as a function of frequency; typical values.
Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values.
102 handbook, halfpage |yfs | (mS) |y fs|
MGS372
102 - fs (deg)
handbook, halfpage
10
MCD971
yos (mS) bos
fs 10 10 1
gos
1 10
102
f (MHz)
1 103
10-1 10
102
f (MHz)
103
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.17 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.18 Output admittance as a function of frequency; typical values.
2000 Apr 11
8
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
handbook, halfpage
0
MCD972
crosstalk level (dB) -20
-40
-60
-80
0
200
400
600
800 1000 f (MHz)
Active amplifier: VDS = 5 V; VG2 = 4 V; ID = 15 mA. Non-active amplifier: VDS = VG1-S = 0 V. Source and load impedances: 50 (both amplifiers). Tamb = 25 C.
Fig.19 Crosstalk as a function of frequency: Output level of non-active amplifier related to output level of active amplifier; typical values.
handbook, full pagewidth
VAGC R1 10 k
C1 4.7 nF C3 4.7 nF
C2 RGEN 50 VI R2 50 4.7 nF RG1
DUT
2.2 H
C4 4.7 nF
L1
RL 50
VGG
VDS
MGS315
Fig.20 Cross-modulation test set-up (for one MOS-FET).
2000 Apr 11
9
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 MAGNITUDE (ratio) 0.987 0.981 0.961 0.933 0.899 0.867 0.834 0.805 0.779 0.758 0.740 ANGLE (deg) -5.6 -11.1 -21.9 -32.1 -42.0 -51.1 -59.9 -67.9 -75.7 -82.1 -89.0 s21 MAGNITUDE (ratio) 4.069 4.042 3.926 3.778 3.593 3.412 3.216 3.010 2.804 2.656 2.509 ANGLE (deg) 173.5 167.0 154.4 142.4 130.6 119.6 109.2 99.0 89.2 80.3 69.9 s12 MAGNITUDE (ratio) 0.001 0.002 0.005 0.006 0.007 0.007 0.007 0.006 0.007 0.007 0.009
BF1102; BF1102R
s22 ANGLE (deg) 95.4 81.3 75.8 69.6 65.6 64.4 67.5 78.7 92.7 120.7 125.5 MAGNITUDE (ratio) 0.986 0.983 0.976 0.960 0.945 0.928 0.914 0.901 0.886 0.889 0.890 ANGLE (deg) -3.0 -6.0 -12.0 -17.7 -23.2 -29.1 -34.1 -39.8 -45.1 -49.7 -55.7
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C f (MHz) 800 Fmin (dB) 2 opt (ratio) 0.621 (deg) 61.61 Rn () 25.85
2000 Apr 11
10
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
PACKAGE OUTLINE Plastic surface mounted package; 6 leads
BF1102; BF1102R
SOT363
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT363
REFERENCES IEC JEDEC EIAJ SC-88
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
2000 Apr 11
11
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development
BF1102; BF1102R
DEFINITIONS (1) This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2000 Apr 11
12
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
NOTES
BF1102; BF1102R
2000 Apr 11
13
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
NOTES
BF1102; BF1102R
2000 Apr 11
14
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
NOTES
BF1102; BF1102R
2000 Apr 11
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
603504/03/pp16
Date of release: 2000
Apr 11
Document order number:
9397 750 06919


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